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Differential Input, 555 kSPS 12-Bit ADC in an 8-Lead SOT-23 AD7452
FEATURES
Specified for VDD of 3 V and 5 V Low power at max throughput rate: 3.3 mW max at 555 kSPS with 3 V supplies 7.25 mW max at 555 kSPS with 5 V supplies Fully differential analog input Wide input bandwidth: 70 dB SINAD at 100 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface: SPI(R)/QSPITM/MICROWIRETM/DSP compatible Power-down mode: 1 A max 8-lead SOT-23 package
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN+ T/H VIN- VREF
12-BIT SUCCESSIVE APPROXIMATION ADC
SCLK
AD7452
SDATA CONTROL LOGIC CS
03154-A-001
APPLICATIONS
Transducer interface Battery-powered systems Data acquisition systems Portable instrumentation Motor control
GND
Figure 1.
GENERAL DESCRIPTION
The AD74521 is a 12-bit, high speed, low power, successive approximation (SAR) analog-to-digital converter that features a fully differential analog input. This part operates from a single 3 V or 5 V power supply and features throughput rates up to 555 kSPS. The part contains a low noise, wide bandwidth, differential track-and-hold amplifier (T/H) that can handle input frequencies up to 3.5 MHz. The reference voltage is applied externally to the VREF pin and can be varied from 100 mV to 3.5 V depending on the power supply and what suits the application. The value of the reference voltage determines the common-mode voltage range of the part. With this truly differential input structure and variable reference input, the user can select a variety of input ranges and bias points. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the device to interface with microprocessors or DSPs. The input signals are sampled on the falling edge of CS, and the conversion is also initiated at this point.
The SAR architecture of this part ensures that there are no pipeline delays. The AD7452 uses advanced design techniques to achieve very low power dissipation.
PRODUCT HIGHLIGHTS
1. 2. Operation with Either 3 V or 5 V Power Supplies. High Throughput with Low Power Consumption. With a 3 V supply, the AD7452 offers 3.3 mW max power consumption for 555 kSPS throughput. Fully Differential Analog Input. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. This part also features a shutdown mode to maximize power efficiency at lower throughput rates. Variable Voltage Reference Input. No Pipeline Delay. Accurate Control of the Sampling Instant via a CS Input and Once-Off Conversion Control. ENOB > 8 Bits Typically with 100 mV Reference.
3. 4.
5. 6. 7. 8.
1
Protected by U.S. Patent Number 6,681,332.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD7452 TABLE OF CONTENTS
AD7452-Specifications.................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Terminology ...................................................................................... 8 AD7452-Typical Performance Characteristics .......................... 10 Circuit Information ........................................................................ 13 Converter Operation.................................................................. 13 ADC Transfer Function............................................................. 13 Typical Connection Diagram ................................................... 14 Analog Input ............................................................................... 14 Driving Differential Inputs........................................................ 16 Digital Inputs .............................................................................. 18 Reference ..................................................................................... 18 Single-Ended Operation............................................................ 18 Serial Interface ............................................................................ 19 Modes of Operation ....................................................................... 20 Normal Mode.............................................................................. 20 Power-Down Mode .................................................................... 20 Power-Up Time .......................................................................... 21 Power vs. Throughput Rate....................................................... 22 Microprocessor and DSP Interfacing ...................................... 22 Application Hints ....................................................................... 24 Evaluating the AD7452's Performance .................................... 24 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25
REVISION HISTORY
2/04--Data Sheet changed from Rev. A to Rev. B Added Patent Note ....................................................................... 1 2/04--Data Sheet changed from Rev. 0 to Rev. A Updated Formatting .......................................................Universal Changes to Applications section................................................. 1 Changes to General Description ................................................ 1 Changes to Specifications ............................................................ 4 Changes to Timing Specifications .............................................. 5 Changes to Timing Example ..................................................... 19 9/03--Revision 0: Initial Version
Rev. B | Page 2 of 28
AD7452 AD7452-SPECIFICATIONS
VDD = 2.7 V to 3.6 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.0 V; VDD = 4.75 V to 5.25 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.5 V; VCM1 = VREF; TA = TMIN to TMAX, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD)3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise3 Intermodulation Distortion (IMD)3 Second-Order Terms Third-Order Terms Aperture Delay3 Aperture Jitter3 Full Power Bandwidth3, 4 DC ACCURACY Resolution Integral Nonlinearity (INL) 3 Differential Nonlinearity (DNL) 3 Zero-Code Error3 Positive Gain Error3 Negative Gain Error3 ANALOG INPUT Full-Scale Input Span Absolute Input Voltage VIN+ VIN- DC Leakage Current Input Capacitance REFERENCE INPUT VREF Input Voltage Test Conditions/Comments fIN = 100 kHz VDD = 4.75 V to 5.25 V, -86 dB typ VDD = 2.7 V to 3.6 V, -84 dB typ VDD = 4.75 V to 5.25 V, -86 dB typ VDD = 2.7 V to 3.6 V, -84 dB typ fa = 90 kHz, fb = 110 kHz B Version2 70 -76 -74 -76 -74 -89 -89 5 50 20 2.5 12 1 0.95 6 2 2 VIN+ - VIN- VCM1 VREF/2 VCM1 VREF/2 1 30/10 2.56 2.07 1 10/30 2.4 0.8 1 10 2.8 2.4 0.4 1 10 Twos Complement Unit dB min dB max dB max dB max dB max dB typ dB typ ns typ ps typ MHz typ MHz typ Bits LSB max LSB max LSB max LSB max LSB max V V V A max pF typ V V A max pF typ V min V max A max pF max V min V min V max A max pF max
@ -3 dB @ -0.1 dB
Guaranteed no missed codes to 12 bits
2 x VREF 5 VCM = VREF VCM = VREF When in track/hold VDD = 4.75 V to 5.25 V (1% tolerance for specified performance) VDD = 2.7 V to 3.6 V (1% tolerance for specified performance) When in track/hold
DC Leakage Current VREF Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN 8 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance8 Output Coding
Typically 10 nA, VIN = 0 V or VDD
VDD = 4.75 V to 5.25 V, ISOURCE = 200 A VDD = 2.7 V to 3.6 V, ISOURCE = 200 A ISINK = 200 A
Rev. B | Page 3 of 28
AD7452
Parameter CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time3 Throughput Rate POWER REQUIREMENTS VDD IDD9, 10 Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation Normal Mode (Operational) Full Power-Down Test Conditions/Comments 1.6 s with a 10 MHz SCLK Sine wave input Step input B Version2 16 200 290 555 Unit SCLK cycles ns max ns max kSPS max
Range: 3 V + 20%/-10%; 5 V 5% SCLK on or off VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.6 V SCLK on or off VDD = 5 V, 1.55 mW typ for 100 kSPS9 VDD = 3 V, 0.64 mW typ for 100 kSPS9 VDD = 5 V, SCLK on or off VDD = 3 V, SCLK on or off
2.7/5.25 0.5 1.5 1.2 1 7.25 3.3 5 3
V min/V max mA typ mA max mA max A max mW max mW max W max W max
1 2
Common-mode voltage. The input signal can be centered on a dc common-mode voltage in the range specified in Figure 23 and Figure 24. Temperature ranges as follows: B Version: -40C to +85C. 3 See Terminology section. 4 Analog inputs with slew rates exceeding 27 V/s (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the converter. 5 Because the input spans of VIN+ and VIN- are both VREF and are 180 out of phase, the differential voltage is 2 x VREF. 6 The AD7452 is functional with a reference input from 100 mV; for VDD = 5 V, the reference can range up to 3.5 V. 7 The AD7452 is functional with a reference input from 100 mV; for VDD = 3 V, the reference can range up to 2.2 V. 8 Guaranteed by characterization. 9 See Power vs. Throughput Rate section. 10 Measured with a midscale dc input.
Rev. B | Page 4 of 28
AD7452
TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a 1.6 V voltage level. See Figure 2 and the Serial Interface section. VDD = 2.7 V to 3.6 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.0 V; VDD = 4.75 V to 5.25 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.5 V; VCM1 = VREF; TA = TMIN to TMAX, unless otherwise noted. Table 2.
Parameter fSCLK 2 tCONVERT tQUIET t1 t2 t33 t43 t5 t6 t7 t8 4 tPOWER-UP5 Limit at TMIN, TMAX 10 10 16 x tSCLK 1.6 60 10 10 20 40 0.4 tSCLK 0.4 tSCLK 10 10 35 1 Unit kHz min MHz max s max ns min ns min ns min ns max ns max ns min ns min ns min ns min ns max s max Description
tSCLK = 1/fSCLK Minimum quiet time between the end of a serial read and the next falling edge of CS Minimum CS pulse width CS falling edge to SCLK falling edge setup time Delay from CS falling edge until SDATA three-state disabled Data access time after SCLK falling edge SCLK high pulse width SCLK low pulse width SCLK edge to data valid hold time SCLK falling edge to SDATA three-state enabled SCLK falling edge to SDATA three-state enabled Power-up time from full power-down
t1
CS
t2
SCLK 1 2 3 4
t5
5
tCONVERT
B 13 14 15 16
SDATA
0
0 0 4 LEADING ZEROS
0
DB11
DB10
DB2
DB1
DB0
tQUIET
THREE-STATE
Figure 2. Serial Interface Timing Diagram
1 2
Common-mode voltage. Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V, or 0.4 V or 2.0 V for VDD = 3 V. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the Timing Specifications is the true bus relinquish time of the part and is independent of the bus loading. 5 See Power-Up Time section.
Rev. B | Page 5 of 28
03154-A-002
t3
t4
t7
t6
t8
AD7452 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to GND VIN+ to GND VIN- to GND Digital Input Voltage to GND Digital Output Voltage to GND VREF to GND Input Current to Any Pin Except Supplies1 Operating Temperature Range Commercial (B Version) Storage Temperature Range Junction Temperature JA Thermal Impedance JC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 secs) Infrared (15 secs) ESD Rating -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V 10 mA -40C to +85C -65C to +150C 150C 211.5C/W 91.99C/W 215C 220C 1 kV
TO OUTPUT PIN 1.6V CL 25pF 200A IOH
03154-A-003
1.6mA
IOL
Figure 3. Load Circuit for Digital Output Timing Specifications
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
Transient currents of up to 100 mA will not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 6 of 28
AD7452 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD 1 SCLK 2 SDATA 3 CS 4
8
VREF
Figure 4. 8-Lead SOT-23 Pin Configuration
Table 4. Pin Function Descriptions
Mnemonic VREF Function Reference Input for the AD7452. An external reference must be applied to this input. For a 5 V power supply, the reference is 2.5 V ( 1%) for specified performance. For a 3 V power supply, the reference is 2 V ( 1%) for specified performance. This pin should be decoupled to GND with a capacitor of at least 0.1 F. See the Reference section for more details. Positive Terminal for Differential Analog Input. Negative Terminal for Differential Analog Input. Analog Ground. Ground reference point for all circuitry on the AD7452. All analog input signals and any external reference signal should be referred to this GND voltage. Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7452 and framing the serial data transfer. Serial Data. Logic output. The conversion result from the AD7452 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of conversion data, which are provided MSB first. The output coding is twos complement. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process. Power Supply Input. VDD is 3 V (+20%/-10%) or 5 V ( 5%). This supply should be decoupled to GND with a 0.1 F capacitor and a 10 F tantalum capacitor in parallel.
VIN+ VIN- GND
CS
SDATA
SCLK
VDD
Rev. B | Page 7 of 28
03154-A-004
VIN+ TOP VIEW 6 VIN- (Not to Scale) 5 GND
7
AD7452
AD7452 TERMINOLOGY
Signal-to-(Noise + Distortion) Ratio The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. For the AD7452, it is defined as
The AD7452 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dB.
Aperture Delay
The amount of time from the leading edge of the sampling clock until the ADC actually takes the sample.
Aperture Jitter
THD(dB) = 20 log
V 22 +V 32 +V 42 +V 52 +V 6 2 V1
The sample-to-sample variation in the effective point in time at which the actual sample is taken.
Full Power Bandwidth
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second to the sixth harmonics.
Peak Harmonic or Spurious Noise
The full power bandwidth of an ADC is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 0.1 dB or 3 dB for a full-scale input.
Common-Mode Rejection Ratio (CMRR)
Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak.
Intermodulation Distortion
This is the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the common-mode voltage of VIN+ and VIN- of frequency fS CMRR(dB) = 10 log(Pf/PfS) Pf is the power at the frequency f in the ADC output; PfS is the power at frequency fS in the ADC output.
Integral Nonlinearity (INL)
With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at the sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa - fb), while the third-order terms include (2fa + fb), (2fa - fb), (fa + 2fb) and (fa - 2fb).
The maximum deviation from a straight line passing through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
Zero Code Error
The deviation of the midscale code transition (111...111 to 000...000) from the ideal VIN+ - VIN- (i.e., 0 LSB)
Rev. B | Page 8 of 28
AD7452
Positive Gain Error Power Supply Rejection Ratio (PSRR)
This is the deviation of the last code transition (011...110 to 011...111) from the ideal VIN+ - VIN- (i.e., VREF - 1 LSB), after the zero code error has been adjusted out.
Negative Gain Error
The ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC VDD supply of frequency fS. The frequency of this input varies from 1 kHz to 1 MHz. PSRR(dB) = 10log(Pf/PfS) Pf is the power at frequency f in the ADC output; Pfs is the power at frequency fS in the ADC output.
This is the deviation of the first code transition (100...000 to 100...001) from the ideal VIN+ - VIN- (i.e., -VREF + 1 LSB), after the zero code error has been adjusted out.
Track-and-Hold Acquisition Time
The minimum time required for the track-and-hold amplifier to remain in track mode for its output to reach and settle to within 0.5 LSB of the applied input signal.
Rev. B | Page 9 of 28
AD7452 AD7452-TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, fS = 555 kSPS, fSCLK = 10 MHz, unless otherwise noted.
75 VDD = 5.25V VDD = 4.75V -20 70 VDD = 3.6V SINAD (dB) 0 8192 POINT FFT fSAMPLE = 555kSPS fIN = 100kSPS SINAD = 71.7dB THD = -82dB SFDR = -83dB
-40
SNR (dB)
03154-A-005
VDD = 2.7V 65
-60 -80
60
-100 -120 -140 0 100 200 FREQUENCY (kHz)
03154-A-008
55 10 FREQUENCY (kHz)
100
277
277
Figure 5. SINAD vs. Analog Input Frequency for Various Supply Voltages
Figure 8. Dynamic Performance with VDD = 5 V
0 -10 -20
1.0 0.8 0.6
DNL ERROR (LSB)
03154-A-006
-30
CMRR (dB)
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 CODE 3072
03154-A-009
-40 -50 -60 -70 -80 -90 VDD = 5V -100 10 100 1000 FREQUENCY (kHz) VDD = 3V
10000
4096
Figure 6. CMRR vs. Frequency for VDD = 5 V and 3 V
Figure 9. Typical DNL for VDD = 5 V
0 100mV p-p SINE WAVE ON VDD NO DECOUPLING ON VDD -20
1.0 0.8 0.6 0.4
INL ERROR (LSB)
03154-A-007
-40
PSRR (dB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 CODE 3072
03154-A-010
-60
VDD= 3V VDD= 5V
-80
-100
-120 0 100 200 300 400 500 600 700 800 SUPPLY RIPPLE FREQUENCY (kHz)
900 1000
4096
Figure 7. PSRR vs. Supply Ripple Frequency without Supply Decoupling
Figure 10. Typical INL for VDD = 5 V
Rev. B | Page 10 of 28
AD7452
3.0 2.5 2.0 2.0 1.5
CHANGE IN DNL (LSB)
1.5 1.0 POSITIVE DNL 0.5 0
03154-A-011
CHANGE IN INL (LSB)
1.0 0.5 POSITIVE INL
0 -0.5 NEGATIVE INL
03154-A-014
-0.5 -1.0 0 0.5 1.0
-1.5 -2.0 0 0.5 1.0 VREF (V) 1.5 2.0 2.2 2.5
NEGATIVE DNL 1.5 2.0 VREF (V) 2.5 3.0
3.5
Figure 11. Change in DNL vs. VREF for VDD = 5 V
Figure 14. Change in INL vs. VREF for VDD = 3 V
2.5 2.0
8 7
ZERO-CODE ERROR (LSB)
CHANGE IN DNL (LSB)
1.5
6 5 4 3 2 1 0 0 0.5 1.0 1.5 2.0 VREF (V) 2.5 3.0 3.5 VDD = 3V
03154-A-015
VDD = 5V
1.0 POSITIVE DNL 0.5 0
03154-A-012
-0.5 -1.0 0 0.5 1.0
NEGATIVE DNL
1.5 VREF (V)
2.0
2.2
2.5
Figure 12. Change in DNL vs. VREF for VDD = 3 V
Figure 15. Change in Zero-Code Error vs. Reference Voltage VDD = 5 V and 3 V
5 4
12.0 11.5 VDD = 3V VDD = 5V
CHANGE IN INL (LSB)
2 1 0 -1 -2 -3 -4 -5 0 0.5 1.0 1.5 2.0 VREF (V) 2.5 3.0
03154-A-013
EFFECTIVE NUMBER OF BITS
3
11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 0 0.5
POSITIVE INL
NEGATIVE INL
3.5
1.0
1.5 2.0 VREF (V)
2.5
3.0
3.5
Figure 13. Change in INL vs. VREF for VDD = 5 V
Figure 16. Change in ENOB vs. Reference Voltage VDD = 5 V and 3 V
Rev. B | Page 11 of 28
03154-A-016
AD7452
10,000 9,000 8,000 7,000 6,000 5,000 4,000 3,000 2,000 1,000 0 2044
03154-A-017
VIN+ = VIN- 10,000 CONVERSIONS fS = 555kSPS
10,000 CODES
2045
2046 CODE
2047
2048
2049
Figure 17. Histogram of 10,000 Conversions of a DC Input with VDD = 5 V
Rev. B | Page 12 of 28
AD7452 CIRCUIT INFORMATION
The AD7452 is a 12-bit, low power, single-supply, successive approximation analog-to-digital converter (ADC). It can operate with a 5 V or 3 V power supply, and is capable of throughput rates up to 555 kSPS when supplied with a 10 MHz SCLK. It requires an external reference to be applied to the VREF pin, with the value of the reference chosen depending on the power supply and what suits the application. When operated with a 5 V supply, the maximum reference that can be applied is 3.5 V. When operated with a 3 V supply, the maximum reference that can be applied is 2.2 V (see the Reference section). The AD7452 has an on-chip differential track-and-hold amplifier, a successive approximation (SAR) ADC, and a serial interface, housed in an 8-lead SOT-23 package. The serial clock input accesses data from the part and provides the clock source for the successive approximation ADC. The AD7452 features a power-down option for reduced power consumption between conversions. The power-down feature is implemented across the standard serial interface as described in the Modes of Operation section. When the ADC starts a conversion (Figure 19), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC's output code. The output impedances of the sources driving the VIN+ and the VIN- pins must be matched; otherwise, the two inputs will have different settling times, resulting in errors.
CAPACITIVE DAC B VIN+ A A B VREF CS SW1 SW3 VIN- SW2 CS COMPARATOR CAPACITIVE DAC
03154-A-019
CONTROL LOGIC
CONVERTER OPERATION
The AD7452 is a successive approximation ADC based around two capacitive DACs. Figure 18 and Figure 19 show simplified schematics of the ADC in the acquisition and conversion phase, respectively. The ADC is comprised of control logic, an SAR, and two capacitive DACs. In Figure 18 (acquisition phase), SW3 is closed and SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input.
CAPACITIVE DAC B VIN+ A A B CS SW1 SW3 VIN- SW2 VREF CS COMPARATOR CAPACITIVE DAC
03154-A-018
Figure 19. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7452 is twos complement. The designed code transitions occur at successive LSB values (i.e., 1 LSB, 2 LSBs, and so on). The LSB size is 2 x VREF/4096. The ideal transfer characteristic of the AD7452 is shown in Figure 20.
1LSB = 2 x VREF/4096 011...111 011...110
ADC CODE
000...001 000...000 111...111
CONTROL LOGIC
-VREF 1LSB
+ VREF - 1LSB 0 LSB ANALOG INPUT (VIN+ -VIN-)
Figure 18. ADC Acquisition Phase
Figure 20. Ideal Transfer Characteristic
Rev. B | Page 13 of 28
03154-A-020
100...010 100...001 100...000
AD7452
TYPICAL CONNECTION DIAGRAM
Figure 21 shows a typical connection diagram for the AD7452 for both 5 V and 3 V supplies. In this setup, the GND pin is connected to the analog ground plane of the system. The VREF pin is connected to either a 2.5 V or a 2 V decoupled reference source, depending on the power supply, to set up the analog input range. The common-mode voltage has to be set up externally and is the value on which the two inputs are centered. The conversion result is output in a 16-bit word with four leading zeros followed by the MSB of the 12-bit result. For more details on driving the differential inputs and setting up the common mode, refer to the Driving Differential Inputs section.
0.1F 10F 3V/5V SUPPLY SERIAL INTERFACE VDD VREF p-p VREF p-p CM* VIN+ SCLK
The common mode is the average of the two signals, i.e., (VIN+ + VIN-)/2, and is therefore the voltage upon which the two inputs are centered. This results in the span of each input being CM VREF/2. This voltage has to be set up externally, and its range varies with VREF. As the value of VREF increases, the common-mode range decreases. When driving the inputs with an amplifier, the actual common-mode range is determined by the amplifier's output voltage swing. Figure 23 and Figure 24 show how the common-mode range typically varies with VREF for both 5 V and 3 V power supplies. The common mode must be in this range to guarantee the functionality of the AD7452. For ease of use, the common mode can be set up to equal VREF, resulting in the differential signal being VREF centered on VREF. When a conversion takes place, the common mode is rejected, resulting in a virtually noise-free signal of amplitude, -VREF to +VREF, corresponding to the digital codes of 0 to 4096.
AD7452
CM* VIN- VREF
SDATA CS
C/P
4.5 4.0
GND
COMMON-MODE VOLTAGE (V)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 VREF (V) 2.5 3.0
3.25V
03154-A-021
2V/2.5V VREF 0.1F *CM IS THE COMMON-MODE VOLTAGE.
COMMON-MODE RANGE
Figure 21. Typical Connection Diagram
1.75V
03154-A-023
ANALOG INPUT
The analog input of the AD7452 is fully differential. Differential signals have a number of benefits over single-ended signals, including noise immunity based on the device's common-mode rejection, improvements in distortion performance, doubling of the device's available dynamic range, and flexibility in input ranges and bias points. Figure 22 defines the fully differential analog input of the AD7452.
VREF p-p
COMMON-MODE VOLTAGE (V)
3.5
Figure 23. Input Common-Mode Range vs. VREF (VDD = 5 V and VREF (Max) = 3.5 V)
2.5 2V 2.0
VIN+
AD7452
03154-A-022
1.5 COMMON-MODE RANGE 1.0 1V 0.5
03154-A-024
COMMONMODE VOLTAGE
VREF p-p
VIN-
Figure 22. Differential Input Definition
The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN- pins (i.e., VIN+ - VIN-). VIN+ and VIN- are simultaneously driven by two signals, each of amplitude VREF, that are 180 out of phase. The amplitude of the differential signal is therefore -VREF to +VREF peak-to-peak (i.e., 2 xVREF). This is true regardless of the common mode (CM).
0 0 0.25 0.50 0.75 1.00 1.25 VREF (V) 1.50 1.75
2.00
Figure 24. Input Common-Mode Range vs. VREF (VDD = 3 V and VREF (Max) = 2 V)
Rev. B | Page 14 of 28
AD7452
Figure 25 shows examples of the inputs to VIN+ and VIN- for different values of VREF for VDD = 5 V. It also gives the maximum and minimum common-mode voltages for each reference value according to Figure 23. For ac applications, removing high frequency components from the analog input signal through the use of an RC low-pass filter on the relevant analog input pins is recommended. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases, and performance degrades. Figure 27 shows a graph of the THD versus the analog input signal frequency for different source impedances for VDD = 5 V.
0 TA = 25C VDD = 5V -20
REFERENCE = 2V VIN- COMMON-MODE (CM) CMMIN = 1V CMMAX = 4V 2V p-p VIN+
REFERENCE = 2.5V VIN- 2.5V p-p VIN+
03154-A-025
COMMON-MODE (CM) CMMIN = 1.25V CMMAX = 3.75V
Figure 25. Examples of the Analog Inputs to VIN+ and VIN- for Different Values of VREF for VDD = 5 V
Analog Input Structure
Figure 26 shows the equivalent circuit of the analog input structure of the AD7452. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This causes these diodes to become forward-biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. The capacitors, C1 in Figure 26, are typically 4 pF and can primarily be attributed to pin capacitance. The resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 100 . The capacitors C2 are the ADC's sampling capacitors and have a typical capacitance of 16 pF.
VDD
THD (dB)
-40 RIN = 1k RIN = 510 -60
-80 RIN = 300
03154-A-027
-100 10
RIN = 10 100 INPUT FREQUENCY (kHz)
277
Figure 27. THD vs. Analog Input Frequency for Various Source Impedances for VDD = 5 V
D VIN+ C1 D R1
C2
Figure 28 shows a graph of the THD versus the analog input frequency for VDD of 5 V 5% and 3 V +20%/-10%, while sampling at 555 kSPS with an SCLK of 10 MHz. In this case, the source impedance is 10 .
-50 TA = 25C -55
VDD
-60 -65
VIN- C1 D
R1
C2
THD (dB)
03154-A-026
D
-70 -75 VDD = 3.6V -80 -85 -90 10 VDD = 4.75V 100 INPUT FREQUENCY (kHz) VDD = 5.25V
03154-A-028
VDD = 2.7V
Figure 26. Equivalent Analog Input Circuit Conversion Phase--Switches Open; Track Phase--Switches Closed
277
Figure 28. THD vs. Analog Input Frequency for 3 V and 5 V Supply Voltages
Rev. B | Page 15 of 28
AD7452
DRIVING DIFFERENTIAL INPUTS
Differential operation requires that VIN+ and VIN- be simultaneously driven with two equal signals that are 180 out of phase. The common mode must be set up externally and has a range determined by VREF, the power supply, and the particular amplifier used to drive the analog inputs (see Figure 23 and Figure 24). Differential modes of operation with either an ac or a dc input provide the best THD performance over a wide frequency range. Since not all applications have a signal preconditioned for differential operation, there is often a need to perform single-ended-to-differential conversion. a pair of series resistors to minimize the effects of switched capacitance on the front end of the ADCs. The RC low-pass filter on each analog input is recommended in ac applications to remove high frequency components of the analog input. The architecture of the AD8138 results in outputs that are very highly balanced over a wide frequency range without requiring tightly matched external components. If the analog input source being used has zero impedance, all four resistors (RG1, RG2, RF1, RF2) should be the same. If, for example, the source has a 50 impedance and a 50 termination, the value of RG2 should be increased by 25 to balance this parallel impedance on the input and thus ensure that both the positive and negative analog inputs have the same gain (see Figure 29). The outputs of the amplifier are perfectly matched, balanced differential outputs of identical amplitude, and are exactly 180 out of phase. The AD8138 is specified with +3 V, +5 V, and 5 V power supplies, but the best results are obtained when it is supplied by 5 V. The AD8132 is a lower cost device that could also be used in this configuration with slight differences in characteristics to the AD8138 but with similar performance and operation.
Differential Amplifier
An ideal method of applying differential drive to the AD7452 is to use a differential amplifier such as the AD8138. This part can be used as a single-ended-to-differential amplifier or as a differential-to-differential amplifier. In both cases, the analog input needs to be bipolar. It also provides common-mode level shifting and buffering of the bipolar input signal. Figure 29 shows how the AD8138 can be used as a single-ended-todifferential amplifier. The positive and negative outputs of the AD8138 are connected to the respective inputs on the ADC via
R F1 R G1 +2.5V GND -2.5V VOCM 51 R G2 RS*
3.75V 2.5V 1.25V VIN+
AD8138
RS*
C*
AD7452
VIN- C* 3.75V 2.5V 1.25V VREF
RF2
RS-50; C-1nF RG1 = RF1 = RF2 = 499; RG2 = 523
Figure 29. Using the AD8138 as a Single-Ended-to-Differential Amplifier
Rev. B | Page 16 of 28
03154-A-029
*MOUNT AS CLOSE TO THE AD7452 AS POSSIBLE AND ENSURE HIGH PRECISION Rs AND Cs ARE USED.
EXTERNAL VREF (2.5V)
AD7452
Op Amp Pair
An op amp pair can be used to directly couple a differential signal to the AD7452. The circuit configurations shown in Figure 30 and Figure 31 show how a dual op amp can be used to convert a single-ended signal into a differential signal for both a bipolar and unipolar input signal, respectively. The voltage applied to Point A sets up the common-mode voltage. In both diagrams, it is connected in some way to the reference, but any value in the common-mode range can be input here to set up the common mode. The AD8022 is a suitable dual op amp that could be used in this configuration to provide differential drive to the AD7452. Care must be taken when choosing the op amp because the selection depends on the required power supply and the system performance objectives. The driver circuits in Figure 30 and Figure 31 are optimized for dc coupling applications that require optimum distortion performance. The differential op amp driver circuit in Figure 30 is configured to convert and level shift a single-ended, ground-referenced (bipolar) signal to a differential signal centered at the VREF level of the ADC. The circuit configuration shown in Figure 31 converts a unipolar, single-ended signal into a differential signal.
VREF GND V- 220 220 V+ VIN- VIN+ 220 2 x VREF p-p 390 V+ 27 VDD
AD7452
VREF
A V- 10k
27 0.1F
EXTERNAL VREF
Figure 31. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal into a Differential Signal
RF Transformer
In systems that do not need to be dc-coupled, an RF transformer with a center tap offers a good solution for generating differential inputs. Figure 32 shows how a transformer is used for single-ended-to-differential conversion. It provides the benefits of operating the ADC in the differential mode without contributing additional noise and distortion. An RF transformer also has the benefit of providing electrical isolation between the signal source and the ADC. A transformer can be used for most ac applications. The center tap is used to shift the differential signal to the common-mode level required; in this case, it is connected to the reference so the common-mode level is the value of the reference.
3.75V 2.5V 1.25V R R VIN+
220 2 x VREF p-p GND 390 V+ 27 V- 220 220 220 V+ A V- 10k
03154-A-030
VDD
VIN+
AD7452
VIN-
C R
AD7452
VIN- 3.75V 2.5V 1.25V VREF
VREF
27 0.1F
EXTERNAL VREF
EXTERNAL VREF (2.5 V)
Figure 30. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal into a Differential Signal
Figure 32. Using an RF Transformer to Generate Differential Inputs
Rev. B | Page 17 of 28
03154-A-032
20k
03154-A-031
AD7452
DIGITAL INPUTS
The digital inputs applied to the AD7452 are not limited by the maximum ratings, which limit the analog limits. Instead the digital inputs applied, i.e., CS and SCLK, can go to 7 V and are not restricted by the VDD + 0.3 V limits as on the analog input. The main advantage of the inputs being unrestricted to the VDD + 0.3 V limit is that power supply sequencing issues are avoided. If CS and SCLK are applied before VDD, there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V was applied prior to VDD. These examples show that the maximum reference applied to the AD7452 is directly dependent on the value applied to VDD. The value of the reference sets the analog input span and the common-mode voltage range. Errors in the reference source result in gain errors in the AD7452 transfer function and add to specified full-scale errors on the part. A 0.1 F capacitor should be used to decouple the VREF pin to GND. Figure 33 shows a typical connection diagram for the VREF pin.
VDD
REFERENCE
An external reference source is required to supply the reference to the AD7452. This reference input can range from 100 mV to 3.5 V. With a 5 V power supply, the specified reference is 2.5 V and the maximum reference is 3.5 V. With a 3 V power supply, the specified reference is 2 V and the maximum reference is 2.2 V. In both cases, the reference is functional from 100 mV. It is important to ensure that when choosing the reference value for a particular application, the maximum analog input range (VIN max) is never greater than VDD + 0.3 V to comply with the maximum ratings of the device. The following two examples calculate the maximum VREF input that can be used when operating the AD7452 at a VDD of 5 V and 3 V, respectively.
NC VDD
1
AD780
OPSEL 8
7 6
AD7452*
NC NC 2.5V NC 0.1F
03154-A-033
VREF
2 VIN 3 TEMP VOUT
0.1F
10nF
0.1F
4 GND
TRIM 5
NC = NO CONNECT *ADDITIONAL PINS OMITTED FOR CLARITY
Figure 33. Typical VREF Connection Diagram for VDD = 5 V
Table 5. Examples of Suitable Voltage References
Reference AD780 ADR421 ADR420 Output Voltage (V) 2.5/3 2.5 2.048 Initial Accuracy (%) 0.04 0.04 0.05 Operating Current (A) 1000 500 500
Example 1
VIN max = VDD + 0.3 VIN max = VREF + VREF/2 If VDD = 5 V, then VIN max = 5.3 V. Therefore 3 x VREF/2 = 5.3 V VREF max = 3.5 V Thus, when operating at VDD = 5 V, the value of VREF can range from 100 mV to a maximum value of 3.5 V. When VDD = 4.75 V, VREF max = 3.17 V.
SINGLE-ENDED OPERATION
When supplied with a 5 V power supply, the AD7452 can handle a single-ended input. The design of this part is optimized for differential operation, so with a single-ended input, performance degrades. Linearity degrades by 0.2 LSB typically, the full-scale errors degrade by 1 LSB typically, and ac performance is not guaranteed. To operate the AD7452 in single-ended mode, the VIN+ input is coupled to the signal source, while the VIN- input is biased to the appropriate voltage corresponding to the midscale code transition. This voltage is the common mode, which is a fixed dc voltage (usually the reference). The VIN+ input swings around this value and should have a voltage span of 2 x VREF to make use of the full dynamic range of the part. The input signal therefore has peak-to-peak values of common mode VREF. If the analog input is unipolar, an op amp in a noninverting unity gain configuration can be used to drive the VIN+ pin. Because the ADC operates from a single supply, it is necessary to level shift ground-based bipolar signals to comply with the input requirements. An op amp can be configured to rescale and level shift the ground-based bipolar signal so it is compatible with the selected input range of the AD7452 (see Figure 34).
Example 2
VIN max = VDD + 0.3 VIN max = VREF + VREF/2 If VDD = 3 V, then VIN max = 3.3 V. Therefore 3 x VREF/2 = 3.3 V VREF max = 2.2 V Thus, when operating at VDD = 3 V, the value of VREF can range from 100 mV to a maximum value of 2.2 V. When VDD = 2.7 V, VREF max = 2 V.
Rev. B | Page 18 of 28
AD7452
R +2.5V 0V -2.5V R VIN R R 5V 2.5V 0V VIN+
AD7452
0.1F VIN- VREF
EXTERNAL VREF (2.5V)
The remaining data is then clocked out on the subsequent SCLK falling edges beginning with the second leading zero. Thus, the first falling clock edge on the serial clock provides the second leading zero. The final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. Once the conversion is complete and the data has been accessed after the 16 clock cycles, it is important to ensure that before the next conversion is initiated, enough time is left to meet the acquisition, and quiet time specifications (see the Timing Example). In applications with a slower SCLK, it may be possible to read in data on each SCLK rising edge, i.e., the first rising edge of SCLK after the CS falling edge would have the leading zero provided and the 15th SCLK edge would have DB0 provided.
Figure 34. Applying a Bipolar Single-Ended Input to the AD7452
SERIAL INTERFACE
Figure 2 shows a detailed timing diagram for the serial interface of the AD7452. The serial clock provides the conversion clock and also controls the transfer of data from the device during conversion. CS initiates the conversion process and frames the data transfer. The falling edge of CS puts the track-and-hold into hold mode and takes the bus out of three-state. The analog input is sampled and the conversion is initiated at this point. The conversion requires 16 SCLK cycles to complete. Once 13 SCLK falling edges have occurred, the track-and-hold goes back into track on the next SCLK rising edge, as shown at Point B in Figure 2. On the 16th SCLK falling edge, the SDATA line goes back into three-state. If the rising edge of CS occurs before 16 SCLKs have elapsed, the conversion is terminated and the SDATA line goes back into three-state. The conversion result from the AD7452 is provided on the SDATA output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7452 consists of four leading zeros followed by 12 bits of conversion data provided MSB first. The output coding is twos complement. Sixteen serial clock cycles are required to perform a conversion and access data from the AD7452. CS going low provides the first leading zero to be read in by the microcontroller or DSP.
CS 10ns
03154-A-034
Timing Example
Having FSCLK = 10 MHz and a throughput rate of 555 kSPS gives a cycle time of 1/Throughput = 1/555,000 = 1.8 s A cycle consists of t2 + 12.5(1/FSCLK) + tACQ = 1.8 s Therefore, if t2 = 10 ns 10 ns + 12.5(1/10 MHz) + tACQ = 1.8 s tACQ = 540 ns This 540 ns satisfies the requirement of 290 ns for tACQ. From Figure 35, tACQ comprises 2.5(1/FSCLK) + t8 + tQUIET where t8 = 35 ns. This allows a value of 255 ns for tQUIET, satisfying the minimum requirement of 60 ns.
t2
SCLK 1 2 3 4
t5
5
tCONVERT
13 14 15 16
t6
t8 tACQUISITION
03154-A-035
tQUIET
12.5(1/FSCLK) 1/THROUGHPUT
Figure 35. Serial Interface Timing Example
Rev. B | Page 19 of 28
AD7452 MODES OF OPERATION
The mode of operation of the AD7452 is selected by controlling the logic state of the CS signal during a conversion. There are two possible modes of operation, normal and power-down. The point at which CS is pulled high after the conversion has been initiated determines whether or not the AD7452 enters the power-down mode. Similarly, if already in power-down, CS controls whether the device returns to normal operation or remains in power-down. These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements.
POWER-DOWN MODE
This mode is intended for use in applications where slower throughput rates are required; either the ADC is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and the ADC is then powered down for a relatively long duration between these bursts of several conversions. When the AD7452 is in powerdown mode, all analog circuitry is powered down. To enter power-down mode, the conversion process must be interrupted by bringing CS high anywhere after the second falling edge of SCLK, and before the 10th falling edge of SCLK, as shown in Figure 37.
CS 12 10
03154-A-037
NORMAL MODE
This mode is intended for fastest throughput rate performance. The user does not have to worry about any power-up times with the AD7452 remaining fully powered up all the time. Figure 36 shows the general diagram of the AD7452's operation in this mode. The conversion is initiated on the falling edge of CS, as described in the Serial Interface section. To ensure that the part remains fully powered up, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high any time after the 10th SCLK falling edge, but before the 16th SCLK falling edge, the part remains powered up but the conversion is terminated and SDATA goes back into three-state. Sixteen serial clock cycles are required to complete the conversion and access the complete conversion result. CS may idle high until the next conversion or may idle low until sometime prior to the next conversion. Once a data transfer is complete, i.e., when SDATA has returned to three-state, another conversion can be initiated after the quiet time, tQUIET, has elapsed by again bringing CS low.
CS 1 SCLK
03154-A-036
SCLK
SDATA
THREE-STATE
Figure 37. Entering Power-Down Mode
Once CS has been brought high in this window of SCLKs, the part enters power-down, the conversion that was initiated by the falling edge of CS is terminated, and SDATA goes back into three-state. The time from the rising edge of CS to SDATA three-state enabled is never greater than t8 (refer to the Timing Specifications). If CS is brought high before the second SCLK falling edge, the part remains in normal mode and does not power down. This avoids accidental power-down due to glitches on the CS line. In order to exit this mode of operation and power up the AD7452 again, a dummy conversion is performed. On the falling edge of CS, the device begins to power up and continues to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device is fully powered up after 1 s has elapsed and, as shown in Figure 38, valid data results from the next conversion. If CS is brought high before the 10th falling edge of SCLK, the AD7452 again goes back into power-down. This avoids accidental power-up due to glitches on the CS line or an inadvertent burst of eight SCLK cycles while CS is low. So although the device may begin to power up on the falling edge of CS, it again powers down on the rising edge of CS as long as it occurs before the 10th SCLK falling edge.
10
16
SDATA
4 LEADING ZEROS + CONVERSION RESULT
Figure 36. Normal Mode Operation
Rev. B | Page 20 of 28
AD7452
POWER-UP TIME
The power-up time of the AD7452 is typically 1 s, which means that with any SCLK frequency up to 10 MHz, one dummy cycle is always sufficient to allow the device to power up. Once the dummy cycle is complete, the ADC is fully powered up and the input signal will be acquired properly. The quiet time, tQUIET, must still be allowed from the point at which the bus goes back into three-state after the dummy conversion to the next falling edge of CS. When running at the maximum throughput rate of 555 kSPS, the AD7452 powers up and acquires a signal within 0.5 LSB in one dummy cycle. When powering up from the power-down mode with a dummy cycle, as in Figure 38, the track-and-hold, which was in hold mode while the part was powered down, returns to track mode after the first SCLK edge the part receives after the falling edge of CS. This is shown as Point A in Figure 38. Although at any SCLK frequency one dummy cycle is sufficient to power up the device and acquire VIN, it does not necessarily mean that a full dummy cycle of 16 SCLKs must always elapse to power up the device and acquire VIN fully; 1 s is sufficient to power up the device and acquire the input signal. For example, if a 5 MHz SCLK frequency is applied to the ADC, the cycle time is 3.2 s (i.e., 1/(5 MHz) x 16). In one dummy cycle, 3.2 s, the part is powered up and VIN fully acquired. However, after 1 s with a 5 MHz SCLK, only five SCLK cycles would have elapsed. At this stage, the ADC is fully powered up and the signal acquired. So in this case, CS can be brought high after the 10th SCLK falling edge and brought low again after a time, tQUIET, to initiate the conversion. When power supplies are first applied to the AD7452, the ADC may power up either in power-down mode or in normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. Likewise, if the user wants the part to power up in power-down mode, the dummy cycle may be used to ensure the device is in power-down by executing a cycle such as the one shown in Figure 37. Once supplies are applied to the AD7452, the power-up time is the same as that when powering up from power-down mode. It takes approximately 1 s to power up fully if the part powers up in normal mode. It is not necessary to wait 1 s before executing a dummy cycle to ensure the desired mode of operation. Instead, the dummy cycle can occur directly after power is supplied to the ADC. If the first valid conversion is performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed. As mentioned earlier, when powering up from the power-down mode, the part returns to track mode upon the first SCLK edge applied after the falling edge of CS. However, when the ADC powers up initially after supplies are applied, the track-and-hold is already in track mode. This means if (assuming one has the facility to monitor the ADC supply current) the ADC powers up in the desired mode of operation, and thus a dummy cycle is not required to change the mode, and a dummy cycle is not required to place the track-and-hold into track mode.
tPOWER-UP
CS A SCLK
03154-A-038
PART BEGINS TO POWER UP
THIS PART IS FULLY POWERED UP WITH VIN FULLY ACQUIRED 10 16 1 10 16
1
SDATA
INVALID DATA
VALID DATA
Figure 38. Exiting Power-Down Mode
Rev. B | Page 21 of 28
AD7452
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7452 when not converting, the average power consumption of the ADC decreases at lower throughput rates. Figure 39 shows how, as the throughput rate is reduced, the device remains in its power-down state longer and the average power consumption is reduced accordingly. It shows this for both 5 V and 3 V power supplies. For example, if the AD7452 is operated in continuous sampling mode with a throughput rate of 100 kSPS and an SCLK of 10 MHz, and the device is placed in power-down mode between conversions, the power consumption is calculated as follows: Power Dissipation during Normal Operation = 7.25 mW max (for VDD = 5 V) If the power-up time is one dummy cycle (1.06 s if CS is brought high after the 10th SCLK falling edge and then brought low after the quiet time) and the remaining conversion time is another cycle, i.e., 1.6 s, the AD7452 can be said to dissipate 7.25 mW for 2.66 s during each conversion cycle. If the throughput rate = 100 kSPS, the cycle time = 10 s and the average power dissipated during each cycle is (2.66/10) x 7.25 mW = 1.92 mW For the same scenario, if VDD = 3 V, the power dissipation during normal operation is 3.3 mW max. The AD7452 can now be said to dissipate 3.3 mW for 2.66 s during each conversion cycle. The average power dissipated during each cycle with a throughput rate of 100 kSPS is therefore (2.66/10) x 3.3 mW = 0.88 mW This is how the power numbers in Figure 39 are calculated. For throughput rates above 320 kSPS, it is recommended that the serial clock frequency be reduced for optimum power performance.
100
10
POWER (mW)
VDD = 5V
1 VDD = 3V
0.1
03154-A-039
0.01 0 50 100 150 200 250 THROUGHPUT (kSPS) 300
350
Figure 39. Power vs. Throughput Rate for Power-Down Mode
MICROPROCESSOR AND DSP INTERFACING
The serial interface on the AD7452 allows the part to be directly connected to a range of different microprocessors. This section explains how to interface the AD7452 with some of the more common microcontroller and DSP serial interface protocols.
AD7452 to ADSP-21xx
The ADSP-21xx family of DSPs is interfaced directly to the AD7452 without any glue logic required. The SPORT control register should be set up as follows: TFSW = RFSW = 1, Alternate Framing INVRFS = INVTFS = 1, Active Low Frame Signal DTYPE = 00, Right-Justify Data SLEN = 1111, 16-Bit Data-Words ISCLK = 1, Internal Serial Clock TFSR = RFSR = 1, Frame Every Word IRFS = 0 ITFS = 1 To implement power-down mode, SLEN should be set to 1001 to issue an 8-bit SCLK burst. The connection diagram is shown in Figure 40. The ADSP-21xx has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in alternate framing mode and the SPORT control register is set up as described. The frame synchronization signal generated on the TFS is tied to CS and, as with all signal processing applications, equidistant sampling is necessary. However in this example, the timer interrupt is used to control the sampling rate of the ADC; under certain conditions, equidistant sampling may not be achieved.
This figure assumes a very short time to enter power-down mode. This increases as the burst of clocks used to enter the power-down mode is increased.
Rev. B | Page 22 of 28
AD7452
AD7452*
ADSP-21xx*
AD7452*
SCLK
TMS320C5x/ C54x*
CLKx CLKR
SCLK SDATA CS
SCLK DR RFS
03154-A-040
SDATA CS
DR FSx FSR
03154-A-041 03154-A-042
TFS
*ADDITIONAL PINS REMOVED FOR CLARITY
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 40. Interfacing to the ADSP-21xx
Figure 41. Interfacing to the TMS320C5x/C54x
The timer registers, for example, are loaded with a value that provides an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and therefore the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given (i.e., AX0 = TX0), the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high again before the transmission starts. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, the data may be transmitted or it may wait until the next clock edge. For example, the ADSP-2111 has a master clock frequency of 16 MHz. If the SCLKDIV register is loaded with the value 3, an SCLK of 2 MHz is obtained and eight master clock periods elapse for every SCLK period. If the timer registers are loaded with the value 803, 100.5 SCLKs occur between interrupts and subsequently between transmit instructions. This situation results in nonequidistant sampling because the transmit instruction is occurring on an SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, equidistant sampling is implemented by the DSP.
AD7452 to DSP56xxx
The connection diagram in Figure 42 shows how the AD7452 can be connected to the SSI (synchronous serial interface) of the DSP56xxx family of DSPs from Motorola. The SSI is operated in synchronous mode (SYN bit in CRB = 1) with internally generated 1-word frame sync for both Tx and Rx (Bits FSL1 = 0 and FSL0 = 0 in CRB). Set the word length to 16 by setting Bits WL1 = 1 and WL0 = 0 in CRA. To implement power-down mode on the AD7452, the word length can be changed to eight bits by setting Bits WL1 = 0 and WL0 = 0 in CRA. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the DSP56xxx provides equidistant sampling.
AD7452*
DSP56xxx*
SCLK SDATA CS
SCLK SRD SR2
*ADDITIONAL PINS REMOVED FOR CLARITY
AD7452 to TMS320C5x/C54x
The serial interface on the TMS320C5x/C54x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7452. The CS input allows easy interfacing between the TMS320C5x/C54x and the AD7452 without any glue logic required. The serial port of the TMS320C5x/C54x is set up to operate in burst mode with internal CLKx (Tx serial clock) and FSx (Tx frame sync). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1, and TxM = 1. The format bit, FO, may be set to 1 to set the word length to eight bits in order to implement the power-down mode on the AD7452. The connection diagram is shown in Figure 41. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the TMS320C5x/C54x provides equidistant sampling.
Figure 42. Interfacing to the DSP56xxx
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AD7452
APPLICATION HINTS
Grounding and Layout
The printed circuit board that houses the AD7452 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should be joined in only one place, a star ground point established as close as possible to the GND pin on the AD7452. Avoid running digital lines under the device because this couples noise onto the die. The analog ground plane should be allowed to run under the AD7452 to avoid noise coupling. The power supply lines to the AD7452 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10 F tantalum capacitors in parallel with 0.1 F capacitors to GND. To achieve the best from these decoupling components, place them as close to the device as possible.
EVALUATING THE AD7452'S PERFORMANCE
The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the evaluation board controller. The evaluation board controller can be used in conjunction with the AD7452 evaluation board, as well as many other Analog Devices evaluation boards ending with the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7452. The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7452. For more information, see the AD7452 application note that accompanies the evaluation kit.
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AD7452 OUTLINE DIMENSIONS
2.90 BSC
8
7
6
5
1.60 BSC
1 2 3 4
2.80 BSC
PIN 1 0.65 BSC 1.30 1.15 0.90 1.95 BSC
1.45 MAX
0.22 0.08 8 4 0
0.15 MAX
0.38 0.22
SEATING PLANE
0.60 0.45 0.30
COMPLIANT TO JEDEC STANDARDS MO-178BA
Figure 43. 8-Lead Small Outline Transistor Package [SOT-23] (RT-8) Dimensions shown in millimeters
ORDERING GUIDE
Model AD7452BRT-R2 AD7452BRT-REEL7 EVAL-AD7452CB3 EVAL-CONTROL BRD24 Temperature Range -40C to +85C -40C to +85C Linearity Error (LSB)1 1 1 Package Option2 RT-8 RT-8 Evaluation Board Controller Board Branding C07 C07
1 2 3
Linearity error here refers to integral nonlinearity error. RT = SOT-23. This can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes. 4 Evaluation board controller. This board is a complete unit allowing a PC to control and communicate with all Analog Devices' evaluation boards ending in the CB designator. For a complete evaluation kit, you need to order the ADC evaluation board, i.e., EVAL-AD7452CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the see the AD7452 application note that accompanies the evaluation kit for more information.
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AD7452 NOTES
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AD7452 NOTES
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AD7452 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03154-0-2/04(B)
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